This page presents general information and tips for using the LM555 timer and devices with other letter prefixes. There will be minor internal circuitry differences between 555 timer IC's from the various manufacturers but they all should be useable for the circuits on this page.
If you would like to use any of these ideas, do some testing before using the LM555 or LM556 timer in an actual circuit.
Many of the circuits on this page can easily be made with various logic circuit ICs. One advantage to using a 556 timer for these circuits is their high current, bipolar outputs.
Some of the circuits on this page were developed just to see if they would work and have no intended use.
The menu below links to various sections of this page that relate to the items in the index. New additions appear at the bottom of the list.
Applicable Timers For This Page
TRIGGER, THRESHOLD, RESET and CONTROL Input Notes
LM555 - Monostable Oscillator Calculator
LM555 - Astable Oscillator Calculator + Capacitor Calculator
Basic Circuits For The LM555 Timer
Triggering And Timing Helpers For Monostable Timers
Controlling Circuits For LM555 Timers
Atypical Circuits For The LM555 Timer
LM556 Timers with Complimentary or Push-Pull Outputs
Interlocked Monostable Timers - Updated January 2017
Power-Up Reset For Monostable Timers
Cross Canceling For Monostable Timers
Reset/Set - Flip-Flop Made With A LM556 Timer
Using The LM555 As A Voltage Comparator Or Schmitt Trigger
50% Output Duty Cycle (Variable)
Bipolar LED Driver
Electronic Time Constant Control
Voltage Controlled Pulse Width Oscillator
Sweeping Output Siren
D Type Flip-Flop Made With A LM556 Timer
Time Delay Circuits
Variable Period Oscillator (CD4017)
Missing Pulse Detectors / Negative Recovery Circuits
50% Output Duty Cycle (Fixed) Using Logic Devices
Three Stage Cycling Timer Circuit (Traffic Light Circuit)
RESET Input - Currents And Voltages
555 Timer Current Draws
555 Timer Output Section
Power ON Delay Circuits
Power OFF Delay Circuits - Updated February 17
Average 51.5 % Output Duty Cycle Using A 555 Timer
Driving Loads Of Greater Than 15 Volts Or 200 Milliamps
'N' Steps And Stop Circuit (CD4017)
Multiple - Monostable Trigger Inputs
Timer Output Voltage Losses
RC Delayed Timer Triggering
Threshold Terminal Current Limiting
Fixed Frequency / Variable Duty Cycle Oscillator
Reset/Set Bistable Using One LM555 Timer
Start Cycle Charge Time Reduction
Synchronous / Asynchronous Flasher Circuit - Added January 2017
Timed Release - 3 Light Railroad Signal Circuit - Added January 2017
All of the information on this page can also be applied to all bipolar versions of the 555 timer.
All of the information on this page can be applied to the low current, CMOS versions of the 555 timer.
However, the CMOS versions of the 555 have a lower output current rating and may not be able to drive some loads. Also, the outputs of some CMOS timers can source more current than they can sink.
This page does not apply the LM558 - Quad Timer IC which is significantly different when compared to the 555 and 556 timers. The differences include:
(1) 558 timers have open collector outputs with a 100 milliamp current capacity while 555 and 556 timers have bipolar outputs with a 200 milliamp capacity.
(2) The TRIGGER input of 558 timers is EDGE Triggered while the TRIGGER input of 555 and 556 timers are LEVEL Triggered.
(3) Individual LM558 timers cannot operate in an astable mode. Two timers must be connected in a loop to make an astable oscillator.
EDGE Triggered - means that the change in the output state of the timer is caused by a quickly falling or rising voltage at the input terminal. If the input voltage changes too slowly the output will not switch states.
LEVEL Triggered - means that the change in the output state of the timer is caused when the voltage at an input terminal falls bellow or rises above its set level. The rate at which the voltage changes is not important.
The THRESHOLD input terminals for the 555, 556 and 558 timers are all LEVEL triggered.
Print the diagram in the centre of a sheet of paper create a circuit using the ICs pin locations.
Print the diagram in the centre of a sheet of paper and create a circuit using the ICs pin locations.
The TRIGGER and THRESHOLD inputs respond to voltage levels but are not the identical.
The TRIGGER input is safely operated between 0 and the supply voltage.
The THRESHOLD input causes the output of the timer to go LOW when the voltage level goes above 2/3rds of the supply voltage (Vcc).
The THRESHOLD input is safely operated between 0 and 2/3rds of the supply voltage.
Due to the internal circuitry of the timer the THRESHOLD can rise to slightly above 2/3rds of the supply voltage. Any extra current is drained away through the IC.
A low TRIGGER input overrides a high THRESHOLD input.
The THRESHOLD input may malfunction and the timer could be damaged if it is exposed directly to the supply voltage.
If there is a possibility that the THRESHOLD input could be exposed to voltages greater than 2/3rds of the supply voltage, a 1,000 ohm or greater resistor should be placed in series with the THRESHOLD input to prevent excessive current from flowing into this input. This resistor is included in some of the circuit shown on this page.
Most of the circuits at this web site that use the LM555 and LM556 timer do not show connections for the RESET and CONTROL inputs. This was done in order to keep the schematics as simple as possible.
If the RESET input of a 555 or 556 timer is not going to be used, it is normal practice to connect the input to the supply voltage. If the RESET input is left unconnected the operation of the timer will not be affected, however, the RESET of CMOS version of these timers should not be left unconnected as the inputs of these devices are more sensitive and this may cause problems.
For most low speed Astable applications the RESET input can be connected to the CONTROL input if connection to the supply voltage is inconvenient. The operation of the timer will not be affected by his connection.
In many cases the CONTROL input does not require a bypass capacitor if a well regulated power supply is used. However, it is good practice to place a 0.1 microfarad (C2) capacitor at this input to minimize voltage variations during transitions of the timer's output transistors.
It is also good practice to place a 0.1uF bypass capacitor (C1) across the power supply and located as close to the IC as possible. This will also reduce voltage swings when the output transistors of the timer change states.
Note - If the period of the power supply variations is short when compared to the period of the timer, the overall effect of C2 is reduced.
For example; If the power supply - ripple voltage is 120 Hz and the oscillator frequency is 1000 Hz then C2 will have greater benefit than if the oscillator frequency is 10 Hz.
Therefore, at low astable frequencies or long monostable times the effectiveness of a capacitor at the CONTROL input is less than at higher frequencies and short pulse times.
Data sheets for the 555 Timer use the value 1.44 and 0.693 as constants in the timing calculations depending on the way in which the equation was written. While these numbers are not exact reciprocals of one another they are close enough to be used without concern.
For ease of use, the calculators on this page have capacitor values entered in microfarads. This value is multiplied by the calculator to produce the correct result. (1uF = 0.000,001F = 1-6F)
NOTE: The leakage currents of electrolytic capacitors will affect the actual output results of the timers. To compensate for leakage it is often better to use a higher value capacitor and lower value resistors in the timer circuits.
NOTE: The leakage currents of electrolytic capacitors will affect the actual output results of the timers. To compensate for leakage it is often better to use a higher value capacitor and lower value resistors in the timer circuits.
The next calculator can find the capacitance needed for a particular output frequency if the values of R1 and R2 are known.
The following diagrams show some basic circuits and calculations for the LM555 timer.
Circuit 5 has a trigger input that can remain closed and still allow the timer to complete its cycle. This means that the trigger input pulse can be longer than the output pulse.
The LM555 timer and the dual timer LM556 are basis of many model railroad circuit but the sensitivity of the TRIGGER input creates many false triggering problems, particularly if the trigger wires are long. (The 555 timer can oscillate at up to 1 megahertz meaning that the trigger and reset times must be significantly less that 1 millionth of a second.)
The addition of a 470K ohm resistor and a 0.1uF capacitor at the TRIGGER input (Pin 2) will provide a delay of approximately 1/20th of a second from the time the input goes to zero volts until the trigger threshold of 1/3Vcc is reached. This short delay can eliminate false triggering in most cases and if the problem persists the value of the capacitor and/or resistor can be increased as needed.
The following schematic shows two additions to the basic 555 timer circuit. One reduces the trigger sensitivity and the other will double the output pulse duration without increasing the values of R1 and C1.
Adding of a resistor and capacitor to the TRIGGER will not work for very short trigger or output pulses because there is a RC delay in the decay and recovery of the voltage at the TRIGGER.
The value of the 0.1uF capacitor at the trigger input can be made larger to further delay the triggering of the timer when the input goes LOW. Lower values can be used in place of the 470K resistor as well.
The second addition is a helper that will extend the timers output duration without having to use large values of R1 and/or C1. Connecting a 1.8K ohm resistor between the supply voltage and pin 5 of the 555 timer chip the output pulse duration will be approximately doubled.
The boxed in area of the drawing shows the internal circuit at pin 5 of the timer with the 1.8K resistor added. The voltage at pin 5 will be increased from 0.66Vcc to 0.88Vcc which is approximately equal to the voltage across the capacitor after two time constants*. This allows the same output time to be achieved with a smaller resistance or capacitance value thus reducing the error caused by the capacitor leakage current. Conversely, for a given value of R1 and C1, the output time will be doubled by the addition of the resistor at Pin 5.
* - One time constant is equal to R (Ohms) times C (Farads) in seconds. In terms of voltage, one time constant is equal to a rise in voltage across the capacitor from 0 to 63.2 percent its maximum voltage. (1uF = 0.000,001F = 1 X 10-6F)
The trigger and reset voltage levels of the timer will also be increased with the addition of the resistor to pin 5 but this should have no effect in most applications.
To achieve long output times, electrolytic capacitors are often used for C1 and the value of R1 can be as high as 1 Megohm. However with high resistance values for R1 the leakage current of the timing capacitor (C1) becomes a significant factor in the operation of the timer.
The circuit will run much longer than expected and may never time out if the leakage current is equal to the current through the resistor at some voltage. Tantalum capacitors could be used as they have very low leakage currents but these are expensive and not available in large capacitance values.
Adding a resistor to the CONTROL input is not an ideal solution to solving long duration timing situations but should work for pulse times of less than ten minutes.
The following method allows the timer to be triggered by a normally closed switch. This would be useful in applications such as intrusion alarms where the protection circuit is broken if a window or door is opened
The following diagrams show some methods of using one-shot timer to control an astable oscillator.
The following diagrams show some unusual circuits for the LM555 timer. These circuits were developed to provide certain functions that are not typically associated with this device.
Overall, these circuits demonstrate the flexibility of the 555 and 556 timer integrated circuits.
The parts values in these circuits were selected for testing purposes and can be adjusted to suit the needs of a particular application as long as the normal operating parameters of the LM555 are maintained.
Before using any of these circuits for specific applications, testing to determine the best values for the components and the practicality of their use.
In the next circuit an LM556 - dual timer IC is configured so that the output of the second timer is 180 degrees out of phase with the first.
This is done by connecting the OUTPUT of timer A to the TRIGGER and THRESHOLD inputs of timer B. The 10K ohm resistor limits the current that can flow into the THRESHOLD input of timer B.
Due to the ability of the timers to source or sink current, the current from one timers output can flow into the other timer's output depending on which output is HIGH or LOW. The typical output conditions that are referenced to ground or supply are also available and in fact all three could be used at the same time.
Circuits for both Astable and Monostable versions of this method are shown on the diagram.
Timer B in this method acts as a voltage comparator and has no timing function. It is a slave to timer A.
Normal triggering methods and period lengths are not affected.
Both timer's RESET inputs are available and can be used individually or together.
Due to the unusual nature of this type of circuit testing should be done to determine if it is suitable for the use intended. The circuit is usable at frequencies below 1000 Hz.
In the following circuit the timers are interlocked so that while one timer is running the second timer cannot be triggered.
This circuit produces a quasi logic circuit where the first trigger to go LOW prevents the other timer from being triggered until the first trigger clears and the timer resets.
This is done by connecting the OUTPUT of each timer to the TRIGGER of the other timer through a diode and placing a resistor in each trigger circuit. The resistor prevents short circuiting of the active timer's when the trigger is closed on the reset timer.
This circuit can be expanded to any number of sections but the number of diodes needed increases as shown below:
For a circuit without negative recovery the # of Diodes needed = # of 555s X (# of 555s - 1) or N X (N-1).
For a circuit with negative recovery the # of Diodes needed = # of 555s X (# of 555s - 1) + # of 555s or N X (N-1) + N.
When power is applied, all of the timers will trigger and all outputs will go HIGH. If this is undesirable the Power-Up Reset For 555 Timers circuit could be added.
Normal triggering and timing lengths are not affected by this method.
Monostable 555 timer circuits will automatically trigger and start a timing cycle when power is applied to the circuit. The timer's internal circuitry is largely responsible for this triggering but it is also caused stray or installed capacitance at the TRIGGER input of the timer.
Stray capacitance can be from a number of sources but is typically from the wires that connect a push button used to trigger the timer.
Triggering at power-up can be a undesirable if the output's period is long and there is no way to reset the timer once it has been triggered.
To prevent timer from starting at power up, a simple resistor, capacitor and transistor circuit can be connected to the timer's RESET input so that the timer is automatically held in RESET by transistor, Q1, until C1 is almost fully charged.
The length of the resetting period can roughly be determined by R1 X C1 X 3 .
The example circuit shows a monostable oscillator but the method could also temporarily hold an astable 555 oscillator in a reset condition at power-up.
The following circuit is another method of stopping the timing cycle at power-up. In this case, a pulse is sent to the THRESHOLD input which stops the timing cycle when the power is applied.
The following diagram shows a method that allows one LM555 timer to RESET another timer so that, for example, if timer 'A' is running; When timer B is triggered, timer A will be reset.
This means that only one timer can be running at a time.
As with the 'Power-Up Reset For Monostable Timers' circuit above, when the power is applied to the circuit both timers are RESET.
Normal triggering and timing lengths should not be affected by this method.
The trigger switch of the running timer must be OPEN for the RESET to occur.
The next circuit is for a hybrid - SET / RESET type of logic Flip-Flop that is constructed from an LM556 - Dual Timer.
The design is crude but effective for very low speed applications. Its greatest asset is that the outputs of the LM556 are capable of driving current loads of up to 200 milliamps with a minimal voltage loss.
This circuit was originally developed to drive "Stall Motor" type switch machines that are used on model railroads. These motors operate on 12 volts, or less, and draw approximately 15 milliamps when they are stalled.
Due to the design of the LM556 timer chip there are multiple output options available in this circuit. These include the normal timer outputs which are bipolar and the DISCHARGE inputs, (PINS 1 and 13), that are open collector circuits.
The following diagram is for a test version of the LM556 Flip-Flop circuit used to create a "Truth Table" that shows the OUTPUT states for a given INPUT state.
Because there are two inputs for each half of the 556 timer, the input voltages must go above and below the TRIGGER voltage and above the THRESHOLD levels for the circuit to operate correctly. Therefore the ratios of R1/R3 and R2/R4 is important but their actual values are not.
Also, the impedance of the inputs must be low enough to allow for these voltage levels to be achieved.
The next diagram has the TRIGGER and THRESHOLD inputs of the timers separated. The basic function is the same as the circuit above but the output can only change when the input inputs are made low.
The next diagram shows basic input options that can be used with the LM556 Flip-Flop circuit. In actual applications the push buttons could be replaced with or supplemented by electronic input devices.
In circuit A the SET and RESET inputs is brought to 0 Volts to change the state of the Flip-Flop.
In circuit B the SET input is switched between 0 Volts and Vcc, the supply voltage, to change the state of the Flip-Flop. The RESET input is unconnected.
In both circuit A and B, when the push buttons are OPEN the Flip-Flop will remain in its last state until the opposite signal is applied to an input.
Circuits A and B also show two methods of connecting the LED's at inputs 1 and 13. The input method in circuit B would not be practical to produce the STATE 3 condition shown in the Truth Table on the previous diagram.
The values of R1 and R2 in this test were 100K ohms. The value of R3 was 22K ohm.
If resistors R1 and R2 are not used the operation of the circuit becomes unstable.
Due to the internal circuitry at THRESHOLD inputs (PINs 6 and 12) of the LM556 timers, resistors R3 and R4 are needed to limit the current that can flow into these inputs. The value of resistors R3 and R4 should be approximately 1/4 the value of resistors R1 and R2 so that the proper voltage ratios for changing states can be achieved.
The R3 resistor is not required if the inputs are not going to be driven to a HIGH state.
The cross coupling of the timers OUTPUT and TRIGGER/THRESHOLD inputs gives the circuit its FLIP-FLOP action and causes the outputs of the timers to be forced alternately HIGH or LOW. This action only applies to states 1 and 2 in the truth table shown above.
For this circuit to have a memory function such as that of a SET / RESET type Flip-Flop the input inputs must float when no input signal is present. They cannot be held HIGH or LOW as is the case with TTL devices.
The maximum current the the outputs of the LM556 timers can source or sink is 200 milliamps.
These circuits do not need a regulated power supply but the voltage should be well filtered.
Any of the LED's in the circuit could be replaced by an optoisolator, small relay or low current DC motor.
The next section shows how an LM555 timer can be used as a voltage comparator or a Scmitt Trigger with a large offset voltage. The 555 timer is not well suited for this application but it is one that is in wide use with model railroaders.
Shown on the schematic is a secondary output that uses the open collector at the DISCHARGE input (Pin 7) of the timer. This output can sink up to 200 milliamps and would be ideal for driving relays.
The main disadvantage to using this circuit is the the large dead-band (1/3Vcc) between upper and lower threshold voltages. An optional resistor, R5, can be added to the circuit to lower and compress the detection voltage range but this only partially alleviates the problem.
The two graphs at the bottom of the diagram show the input voltages at which the OUTPUT of the LM555 will change states. The effect that resistor R5 has on the circuit can be seen in the right hand graph.
The LM555 timer can achieve a 50 percent duty cycle as shown in the next diagram. The duty cycle adjustment range of the give components values is from 42 to 55 percent.
Resistors R1 and R2 were selected first and then resistor R3 was selected to give the best control range based on measurements at the output of the timer.
The major disadvantage of using the LM555 in this manner is that the output frequency changes as the duty cycle changes.
The circuit shown in the next diagram is not an accurate method of producing a 50 percent duty cycle using 555 timers, either bipolar or CMOS types. The circuit can produce a duty cycle that is close to 50 percent but when a load is added to the output of the timer, the voltage drops across its output transistors will increase and the duty cycle will shift.
This circuit uses two timers to drive Bipolar LEDs and shows all of the possible output states.
Two SPDT switches are used to set the input conditions but these could be replaced by electronic controls.
These circuits show methods of changing the operating frequency of astable LM555 timers electronically. Any source that can drive the base of transistor Q1 can control these circuits.
The advantage of changing the value of the timing capacitors is that the duty cycle of the timer is not affected when the frequency is changes.
The basic circuit operates at a frequency determined by R1, R2 and C1 and has a pulse width range of 0 to 100 percent.
The following diagram shows a basic circuit with an open collector output that would require a pull up resistor at its output. The parts values are the nominal values of the components used.
Note: This circuit is not suitable for high frequency operation, especially when using a second timer as the output stage.
The following is a graph of the output pulse width of the basic circuit for a given control voltage input. All measurements were made with a good quality multimeter.
The PLUS and MINUS inputs of IC 2 can be reversed to produce a decreasing pulse width for an increasing control voltage.
The next diagram uses a second LM555 timer as a power output stage for the basic oscillator. The output stage also has an open collector output at the Discharge input, PIN 7, that could be used.
This circuit is a variation of the "Two Tone Siren" that is a standard for the LM555 timer. The circuit allows the output frequency of the B timer to sweep between two frequencies rather than switching abruptly between two frequencies.
NOTE: The Sweeping Output Siren circuit has a limited sweep range and the duty cycle shifts with the changing output frequency.
A better 555 based circuit for a sweeping oscillator would be to adapt the Variable Pulse Width Oscillator in the section above.
A still better choice for a sweeping oscillator is a Voltage Controlled Oscillator (VCO) IC. See this Wikipedia page for basic information on Voltage-controlled oscillators and this datasheet for the LM321.
Other devices include the TTL 74124 Dual Voltage-Controlled Oscillator and the CMOS CD4046B Phase-Locked Loop.
This circuit is a hybrid - D type Flip-Flop that is constructed from an LM556 - Dual Timer integrated circuit. The circuit is essentially an expensive version of the classic - two transistor Flip-Flop but with a bipolar output and a current capacity of 200 milliamps.
Two versions of the circuit are shown. The updated version separates the TRIGGER and THRESHOLD inputs on the timers and is therefore less sensitive to the ratios of the resistors and capacitors at the trigger inputs.
In both versions, each time the push button switch (S1) is closed the outputs of the timers will reverse so that one is HIGH and the other is LOW and vice versa. The D flip-flop the circuit acts as a binary divider.
The classic circuit has some output switching time lag due to the RC time constants at the inputs and the different Trigger and Threshold voltage levels of the timers themselves, this will limit the maximum rate at which the circuit can be switched.
Because there are two switching levels, 1/3rd and 2/3rds of the supply voltage, the 556 timer is not ideally suited for this type of circuit, therefore the capacitance range of the input capacitors for the classic version of the circuit that will work reliably is quite small; between 0.1 and 1.0 microfarads.
This circuit also has some output switching time lag due to the RC time constants at the inputs but is unaffected by the different Trigger and Threshold voltage levels of the timers themselves as these inputs are now separated.
For the updated circuit, the range of capacitors that can be used at the inputs is large and the capacitors could be of different values without affecting the basic operation of the circuit.
In the BiDirectional Time Delay Circuit, the B timer acts more as a Schmitt trigger with a delay than a conventional timer. See section 14 of this page for more detail.
The following CD4017 circuits have not been tested and is presented here as a possibility only. If you experiment with this circuit, please send me any problems found so that the circuit can be updated.
The following circuits are designed to change the duration of each positive output pulse from the astable timer. The circuits use a CD4017 Decade Counter / Decoder to provide nine or ten steps in the cycle.
The first circuit operates with a repeating ten step cycle. Each output pulse is longer than the previous until a count of ten is reached at which time the cycle will repeat.
The second circuit has a nine step cycle that stops at the end of the cycle. The cycle is restarted or reset when the RESET input is briefly made high.
The CD4017 can be configured to give count lengths between 1 and 10. Refer to the timing diagram in the CD4017 data sheet for a better understanding of the IC's operation.
The next schematic shows an alternate arrangement for the timing resistors. This would allow the subsequent output pulses to be of longer and shorter lengths during the cycle.
The next circuit provides nine counts of a normal timing length with the tenth count being longer and then repeating the cycle.
The first circuit is a simple, push button controlled, Negative Recovery timer circuit. Each time that S1 is closed the time remaining in the cycle is reset to zero. If the time does run out, closing S1 will restart the cycle.
The following circuits can detect when a train of pulses stops or become too far apart. They can also be use to keep the timer at its zero count if the input is held in a steady state. This is called 'Negative Recovery'.
The diode across R1 in these circuits causes C1 to quickly discharge when the power to the circuit is switched off. This allows the circuit to be ready for the next cycle more quickly.
The next two circuits in this section produce the same result: The timer must be reset manually if it has timed out.
The only way to achieve a true - 50 percent duty cycle from a 555 timer is to divide the output by 2 with a binary divider such as the 7473 or 7474 TTL logic ICs.
NOTE All three timers in this circuit will start when power is applied, therefore all but the first timer (A) will need to be Reset for the proper cycle order to be started automatically. (See item 10 in the index of this page for a method of resetting the timers.)
The next diagram gives the current from, and the voltage at the RESET inputs of five - 555 timer chips from different manufacturers.
The only conclusion to be drawn here is that the RESET input should be held below 0.3 Volts to ensure that any of the devices is fully reset.
In the transition voltage range of the RESET input mentioned on the diagram, the timers output is neither fully ON or OFF. This can cause high current flows in the timer itself. The voltage at the RESET input should pass through this range as quickly as possible to avoid problems.
The next diagram shows the basic current consumption of 555 timer chips from different manufacturers.
The RESET input current draw illustrates the need for a current limiting resistor as shown in some of the preceding circuits. Some devices will not function properly if the current to the THRESHOLD input is not restricted.
The following is a method of preventing a timer from being re-triggered before a certain time period has elapsed.
The next diagram shows the output section of a National Semiconductor LM555 timer. This type of output can either source or sink current and is typical of 555 and 556 timer IC's.
When the output of the timer is HIGH, it can supply current to a load. When the output of the timer is LOW, it can receive current from a load.
Transistor Q3 is actually connected as a diode with the collector not carrying current. Although a circuit common symbol is shown, the collector is not connected to the ground of the timer.
These circuits will delay the application of power to an external circuit by using mechanical relays or transistors. Other output control devices could also be used.
These circuits are not ideal as the relays are closed when power is supplied to the circuit. This means that the power is supplied to the load for a very short period until the relay can open.
A variation on the Power On delay circuits above is a delay after pulses start arriving.
A resistor could be placed across capacitor C1 so that the timer will be reset if the pulses stop arriving. This resistor should have a resistance of at least three times the value of R1.
These circuits delay the removal of power to an external circuit by using relays or transistors. Other output control devices could also be used to control the load.
The next circuit produces an average duty cycle of 51.5% over the entire resistance range of R2 at a supply voltage of 10 volts.
At a supply voltage of 5 volts the average duty cycle increased to 52.7%. The span of the duty cycle also increased.
The next two circuits allow the 555 timer to drive loads that have a supply voltage that is greater than the 15 volt maximum of 555 timers.
Higher current loads can be driven by transistors with a suitable current capacity and adjusting the base current as needed. Darlington and MOSFET transistors can drive loads of many amps.
The 24 volt supply can be full wave DC and does not need to be filtered. The load's supply voltage could also be lower than the timer's supply voltage.
The next circuit uses the outputs of a CD4017 - Decade Counter to stop a 555 timer at a given step and then wait until the counter is reset.
The next circuit allows a monostable oscillator to have multiple trigger inputs. The timer can be triggered and time out even if one, or more, of the input switches is held closed.
Input signals that arrive before the current output pulse has ended will not be indicated (The timer cannot be retriggered part way through its cycle.)
The schematic shows push buttons as the input but almost any device that causes the voltage to fall quickly can be used, including a bipolar output from another timer.
The next two diagrams show the voltage losses/drops at the outputs of 555 timers when the output is HIGH and LOW. The data can only be used as a relative indication of the losses as other timers and circuits may have smaller or larger losses.
The next circuit uses a Resistor and Capacitor at the TRIGGER input to delay the triggering of the timer. This is largely an extension of the Triggering And Timing Helpers For Monostable Timers in section 5 of this page.
Two recovery schemes are also shown on the diagram.
The THRESHOLD input of 555 and 556 timers do not have internal current limiting. The following diagram shows how the THRESHOLD input's current can be restricted.
If the current to the THRESHOLD input is not restricted the timer may malfunction. The current limiting resistor should be at least 1,000 ohms but can any higher value that is practical for the circuit. Using a higher value resistor will reduce the overall current usage of the entire circuit.
The important thing is for the THRESHOLD input not to be exposed to the supply voltage or other low impedance source such as the output of another 555 timer without limiting its current.
NOTE: Some timers may need the value of the THRESHOLD's current limiting resistor to be greater than 1K for the device to function correctly.
This circuit is designed to produce an output at a fixed frequency and a wide range duty cycle.
The circuit was breadboarded and functioned as shown in the tables on the diagram. The results were good except for a dip in the output frequency near the low end of the duty cycle range.
The next circuit is for a SET / RESET - Bistable circuit constructed using one LM555 timer IC. This circuit does not have a complimentary output. The input options are unconventional as well.
When power is applied to a 555 Astable timer, the first charging period for C1 is longer that the following periods because the timing capacitor must charge from zero volts to 2/3rds of the supply voltage before resetting the timer.
For subsequent periods the voltage on C1 at the start of each charging period is 1/3.rd of the supply voltage when the timer retriggers.
If the charging or total period of the circuit is long the added charging time for the first cycle can be significant.
The addition or RA, RB and DA allows C1 to charge relatively quickly to a voltage near 1/3rd of the supply.
After the initial charging period, RA and RB have no affect on the timer's operation.
Decreasing the values of RA and RB will allow C1 to initially charge more quickly but will use more power as they are made smaller.
This circuit can flash LEDs in unison or at slightly different rates so that the LED flashes appear to move back-and-forth and be in sync occasionally. The parts values are suggestions only.
The circuit will work properly as long as the period of the 556 B timer is longer than that of the 556 A timer. If B's period is to short LED be will turn off to soon in the synchronous mode.
White, LED type license plate lights can be used with this circuit to make an annoying, white, flasher.
This circuit uses time delays to hold the output LEDs at RED or YELLOW for set time periods after the input goes HIGH. When RED and YELLOW are off the output is GREEN.
The two circuits shown are functionally the same but connect the GREEN LED in different ways. Also, the lower circuit uses twice as much LED current when YELLOW is on.
An variation of this circuit can be seen at Timed 3 Light Signal Driver.
The explanations for the circuits on these pages cannot hope to cover every situation on every layout. For this reason be prepared to do some experimenting to get the results you want. This is especially true of circuits such as the "Across Track Infrared Detection" circuits and any other circuit that relies on other than direct electronic inputs, such as switches.
If you use any of these circuit ideas, ask your parts supplier for a copy of the manufacturers data sheets for any components that you have not used before. These sheets contain a wealth of data and circuit design information that no electronic or print article could approach and will save time and perhaps damage to the components themselves. These data sheets can often be found on the web site of the device manufacturers.
Although the circuits are functional, the pages are not meant to be full descriptions of each circuit but rather as guides for adapting them for use by others. If you have any questions or comments please send them to the email address on the Circuit Index page.
16 February, 2017