LM555 Timer Internal Circuit Block Diagram
This page presents general information and some tips when using the LM555 timer. If you would like to use any of these ideas, please take time to do some testing before using them in an actual circuit. All of the solutions on this page can be applied to the LM556 Dual timer chip as well.
Some of these circuits were developed just to see if the concept would work and have no intended use.
The menu below will take you to various sections of this page that relate to the items in the index. Newer additions appear at the bottom of the list.
This page does not cover the LM558 Quad timer IC which has significant differences when compared to the 555 and 556 timers.
These differences include: (1) The output of each 558 timer section is an open collector transistor with a 100 milliamp current capacity while the 555 and 556 timers have bipolar outputs with a 200 milliamp capacity. (2) The TRIGGER input the 558 is EDGE Triggered while the TRIGGER input on the 555 and 556 timers are LEVEL Triggered.
Individual LM558 timers are not designed to operate in an astable mode. (Two timers connected in a loop must be used to make an astable oscillator.)
EDGE Triggered - means that the change in the output state of the IC is caused by a quickly falling or rising input voltage at the input terminal. If the input voltage falls too slowly the output will not change.
LEVEL Triggered - means that the change in the output state of the IC is caused when the voltage at an input terminal falls bellow or rises above a preset level. The rate at which the voltage changes is not important.
The THRESHOLD input terminals for the 555, 556 and 558 timers are all LEVEL triggered.
Print the diagram in the centre of a sheet of paper and then draw a circuit using the ICs pin locations.
Print the diagram in the centre of a sheet of paper and then draw a circuit using the ICs pin locations.
Most of the circuits at this web site that use the LM555 and LM556 timer chips do not show any connections for the "RESET" and "CONTROL" inputs for these devices. This was done in order to keep the schematics as simple as possible.
When the "RESET" terminal is not going to be used it is normal practice to connect this input to the supply voltage. This is especially true of the CMOS version of these timers as the inputs of these devices are very sensitive.
The "RESET" terminal can also be connected to the "CONTROL" terminal without affecting the basic operation of the timer but the timing cycle will be affected as the voltage at the CONTROL terminal will drop slightly.
In many cases the "CONTROL" input does not require a bypass capacitor when a well regulated power supply is used. It is good practice however to place a 0.1 microfarad (C2) or larger capacitor at this terminal.
It is also good practice to place a 0.1uF - bypass capacitor (C1) across the power supply, located as close to the IC as possible. This will reduce voltage spikes when the output transistors of the timer change states.
Note - If the period of the power supply variations is short when compared to the period of the timer, the overall effect of C2 is reduced.
For example; If the power supply - ripple voltage is 120 Hz and the oscillator frequency is 1000 Hz then C2 will have greater benefit than if the oscillator frequency is 10 Hz.
Therefore, at low astable frequencies or long monostable lengths the effectiveness of a capacitor at the CONTROL input is less than at higher frequencies and short pulse times.
Data sheets for the 555 Timer use the value 1.44 and 0.693 as constants in the timing calculations depending on the way in which the equation was written. While these numbers are not exact reciprocals of one another they are close enough to be used without concern.
For ease of use, the calculators on this page have capacitor values entered in microfarads. This value is multiplied by the calculator to produce the correct result. (1uF = 0.000,001F = 1 X 10-6F)
NOTE: The leakage currents of electrolytic capacitors will affect the actual results of these calculations. To compensate, for longer times it is often better to use a higher value capacitors and lower value resistances in circuits.
NOTE: The leakage currents of electrolytic capacitors will affect the actual results of these calculations. To compensate, for longer times it is often better to use a higher value capacitors and lower value resistances in circuits.
The next calculator can find the capacitance needed for a particular output frequency if the values of R1 and R2 are known.
The following diagrams show some basic circuits and calculations for the LM555 timer.
This circuit also has a trigger input that can remain closed but alow the timer to complete its cycle. This means that the trigger input pulse can be longer than the output pulse.
The venerable LM555 timer chip and its twin brothers the LM556 have been cornerstones of model railroad electronics but the sensitivity of the trigger input gives rise to many false triggering problems. The addition of a 470K ohm resistor and a 0.1uF capacitor at the TRIGGER input (Pin 2) will provide a time delay of approximately 1/20th of a second from the time the input goes to zero volts until the trigger threshold is reached (1/3Vcc). This delay can eliminate false triggering in most cases and if the problem persists the value of the capacitor or resistor can be increased.
The following schematic shows two additions to the basic 555 timer circuit. One reduces the trigger sensitivity and the other will double the output pulse duration without increasing the R1 and C1 values.
The addition of a capacitor to the trigger will not work for very short output pulses as there is also a short delay in the recovery of the trigger terminal voltage.
The second addition is a helper that will extend the timers output duration without having to use large values of R1 and/or C1 by connecting a 1.8K ohm resistor between the supply voltage and pin 5 of the 555 timer chip the output pulse duration will be approximately doubled.
The boxed in area of the drawing shows the internal circuit at pin 5 of the timer with the 1.8K resistor added. The voltage at pin 5 will be increased from 0.66Vcc to 0.88Vcc which is approximately equal to the voltage across the capacitor after two time constants*. This allows the same output time to be achieved with a smaller resistance or capacitance value thus reducing the error caused by the capacitor leakage current. Conversely, for a given value of R1 and C1 the output time will be doubled by the addition of the resistor at Pin 5.
* - One time constant is equal to R (Ohms) times C (Farads) in seconds. In terms of voltage, one time constant is equal to a rise in voltage across the capacitor from 0 to 63.2 percent its maximum voltage. (1uF = 0.000,001F = 1 X 10-6F)
The TRIGGER and RESET voltage levels of the timer will also be increased with the addition of the resistor to pin 5 but this should have no effect in most applications.
To achieve long output times electrolytic capacitors are used for C1 and the value of R1 may be as high as 1 Meg. However with high resistance values for R1 the leakage current of the timing capacitor (C1) becomes a significant factor in the operation of the timer.
The circuit will run much longer than expected and may never time out if the leakage current is equal to the current through the resistor at some voltage. Tantalum capacitors could be used as they have very low leakage currents but these are expensive and not available in large capacitance values.
This is not an ideal solution to solving long duration timing situations but should work for run times of less than ten minutes.
The following method allows the timer to be triggered by a normally closed switch if needed. This would be useful in applications such as intrusion alarms where the protection circuit is broken if a window or door is opened
The following diagrams show some methods of using one timer to control a second timer. Some of these are unusual but still practical and can provide ideas for other control schemes.
In the following diagrams, a ONESHOT oscillator controls an ASTABLE oscillator. Three methods are shown.
The following diagrams show some advanced circuits for the LM555 timer. These circuits were developed to provide certain functions that are not usually associated with this device.
The parts values in these circuits were selected for testing purposes and can be adjusted to suit the needs of a particular application as long as the normal operating parameters of the LM555 are maintained.
These circuits should be viewed as experimental. Before using any of them for specific applications they should be tested to determine the best values for the components and the practicality of their use.
In the next circuit an LM556 - dual timer IC is configured so that the output of the second timer is 180 degrees out of phase with the first.
This is done by connecting the OUTPUT of the "A" timer to the TRIGGER and THRESHOLD terminals of the "B" timer. The 10K ohm resistor in this connection limits the current that can flow into the THRESHOLD terminal of the "B" timer.
Due to the current source or sink capability of the timer outputs the current from one timer's output can flow in to the other timers output depending on which output is HIGH or LOW. The usual outputs that are referenced to ground or supply are also available and in fact all three could be used at the same time.
Circuits for both Astable and Monostable versions of this method are shown on the diagram.
Timer "B" in this method acts as a voltage comparator and has no timing function. It is a slave to the "A" timer.
Normal triggering schemes and timing lengths are not affected by this method.
The timer RESET terminals are available and can be used individually or together if desired.
Due to the unusual nature of this type of circuit testing should be done to determine if it is suitable for the use intended. The circuit is usable at frequencies below 1000Hz.
In the following circuit the timers are "Interlocked" so that when one timer is running the second timer cannot be triggered.
This is done by connecting the OUTPUT of each timer to the TRIGGER of the other via a diode and placing a resistor in the trigger circuit. The resistor limits the current that can flow from the opposite timers output when the trigger is closed on the stopped timer.
Normal triggering and timing lengths are not affected by this method.
Typical monostable 555 timer circuits will automatically trigger and start a timing cycle when power is applied to the circuit. Stray or installed capacitance at the TRIGGER terminal of the timer is responsible for this triggering.
The stray capacitance can be from a number of sources but a typical cause is the wires that connect a push button used to start the timer.
In an ideal circuit, where there is no stray capacitance at the TRIGGER input, a small capacitor at the CONTROL terminal can prevent the timer from triggering .
If there is stray or installed capacitance at the TRIGGER terminal, when the power is applied to an LM555 circuit the timer will immediately be triggered and start a cycle. This can be a undesirable if the time is long and there is no other way to stop the cycle.
To prevent timer from starting, a simple RC timing circuit can be added to the timer's RESET terminal so that when power is applied to the circuit, the timer is automatically held RESET by transistor Q1 until C1 is almost fully charged.
The length of the reseting action can roughly be determined by R1 X C1 X 3 .
The example shows a monostable oscillator but the method could also hold an astable 555 oscillator in a reset condition at power-up.
The following circuit is another method of stopping the timing cycle at power-up. In this case, a pulse is sent to the THRESHOLD terminal which stops the timing cycle when the power is applied.
The following diagram shows a method that allows one LM555 timer to RESET another timer so that, for example, if timer 'A' is running; When timer 'B' is activated the 'A' timer is reset.
This means that only one timer can be running at any time.
As with the 'Power-Up Reset For Monostable Timers' circuit above, when the power is applied to the circuit both timers are RESET.
Normal triggering and timing lengths should not be affected by this method.
The trigger switch of the running timer must be OPEN for the RESET to occur.
The circuit on this page is for a hybrid - SET / RESET type of logic Flip-Flop that is constructed from an LM556 - Dual Timer integrated circuit.
The design is crude but effective for very low speed applications. Its greatest asset is that the outputs of the LM556 are capable of driving current loads of up to 200 milliamps with a minimal voltage loss.
This circuit was originally developed to drive "Stall Motor" type switch machines that are used on model railroads. These motors use low voltage DC and pass approximately 15 milliamps when they are in a stalled condition.
Due to the design of the LM556 timer chip there are multiple output options available in this design. These include the normal timer outputs which are bipolar and the 'DISCHARGE' terminals, (PINS 1 and 13), that are open collector circuits.
The following diagram is for a testing version of the circuit used to create a "Truth Table" that shows the OUTPUT states for a given INPUT state.
The next diagram shows the basic input options that can be used with the LM556 Flip-Flop circuit. In actual applications the push buttons would be replaced by or supplemented with electronic input devices.
In CIRCUIT 'A' the SET and RESET inputs would be brought to '0' Volts to change the state of the Flip-Flop.
In CIRCUIT 'B' the SET input would be switched between '0' Volts and the supply voltage to change the state of the Flip-Flop. The RESET terminal is unconnected.
In both CIRCUITS 'A' and 'B' when the push buttons are 'OPEN' the Flip-Flop will remain in its last state until another INPUT signal is applied.
Circuits 'A' and 'B' also show two methods of connecting the LED's at terminals 1 and 3. The method in circuit 'B' would not be practical for the STATE '3' condition shown in the "Truth Table".
The values of R1 and R2 in this test were 100K ohms. The value of R3 was 22K ohm.
If resistors R1 and R2 are not used the operation of the circuit becomes unstable.
The R3 resistors are not required if the inputs are not going to be driven to a HIGH state.
The next section shows how the LM555 timer could be used as a voltage comparator or a wide offset Scmitt Trigger. Applications for which it is not particularly well suited but one that is in wide use with model railroaders.
Shown on the schematic is a secondary output that uses the open collector at the DISCHARGE terminal (Pin 7) of the timer. This output can sink up to 200 milliamps and would be ideal for driving relays.
The main disadvantage to using this circuit is the the large dead-band (1/3Vcc) between upper and lower threshold voltages. An optional resistor, R5, can be added to the circuit to lower and compress the detection voltage range but this only partially alleviates the problem.
The two graphs at the bottom of the diagram show the input voltages at which the OUTPUT of the LM555 will change states. The effect that resistor R5 has on the circuit can be seen in the right hand graph.
The LM555 timer can achieve a 50 percent duty cycle as shown in the next diagram. The duty cycle adjustment range of the give components values is from 42 to 55 percent.
Resistors R1 and R2 were selected first and then resistor R3 was selected to give the best control range based on measurements at the output of the timer.
The major disadvantage of using the LM555 in this manner is that the output frequency changes as the duty cycle changes.
The circuit shown in the following diagram is not an accurate method of producing a 50 percent duty cycle using 555 timers, either bipolar or CMOS types. The circuit can produce a duty cycle that is close to 50 percent but if a load is added to the output the voltage losses across the timer's output transistors will increase and the duty cycle will shift.
This circuit uses two timers to drive Bipolar LEDs and give all of the possible output states.
Two SPDT switches are used to set the input conditions but these could be replaced by electronic controls if desired.
These circuits show methods of changing the operating frequency of astable LM555 timers electronically. Any source that can drive the base of transistor Q1 can control these circuits.
The advantage of using this type of frequency control is that the duty cycle of the timer is not affected when the frequency is changed.
The basic circuit operates at a frequency determined by R1, R2 and C1 and has a pulse width range of 0 to 100 percent.
The following diagram shows a basic circuit with an open collector output that would require a pull up resistor at its output. The parts values are the nominal values of the components used.
Note: This circuit is not suitable for high frequency operation, especially when using a second timer as the output stage.
The following is a graph of the output pulse width of the basic circuit for a given control voltage input. All measurements were made with a good quality multimeter.
The PLUS and MINUS inputs of IC 2 can be reversed to produce a decreasing pulse width for an increasing control voltage.
The next diagram uses a second LM555 timer as a power output stage for the basic oscillator. The output stage also has an open collector output at the Discharge terminal, PIN 7, that could be used.
This circuit is a variation of the "Two Tone" siren that is a standard for the LM555 timer. The circuit allows the output frequency of the 'B' timer to 'sweep' between two frequencies rather than switching abruptly between two fixed frequencies.
This circuit is a hybrid - D type Flip-Flop that is constructed from an LM556 - Dual Timer integrated circuit. The circuit is essentially a High-Tech and overly expensive version of the classic transistor flip-flop.
Each time the push button switch (S1) is closed the outputs of the timers will reverse so that one is HIGH and the other is LOW and vice versa. As with the D flip-flop the circuit acts as a binary divider.
The circuit has some output switching time lag due to the RC time constants at the inputs and the different Trigger and Threshold voltage levels of the timers themselves.
This circuit is not very useful but would make a good Push On / Push Off switch circuit and has a reasonably high sink or source output current level.
The following CD4017 circuits have not been tested and is presented here as a possibility only. If you experiment with this circuit please send me any problems found so that the circuit can be updated.
The following circuits are designed to change the duration of each positive output pulse from the astable timer. The circuits use a CD4017 Decade Counter / Decoder to provide nine or ten steps in the cycle.
The first circuit operates with a repeating ten step cycle. Each output pulse is longer than the previous until a count of ten is reached at which time the cycle will repeat.
The second circuit has a nine step cycle that stops at the end of the cycle. The cycle is restarted or reset when the RESET input is briefly made high.
The CD4017 can be configured to give count lengths between 1 and 10. Refer to the timing diagram in the CD4017 data sheet for a better understanding of the circuit's operation.
The next schematic shows an alternate arrangement of the timing resistors. This would allow the output pulse to be of longer and shorter lengths during the cycle.
The next circuit provides nine counts of a normal timing length with the tenth count being longer and then repeating the cycle.
The first circuit is a simple, push button controlled, Negative Recovery timer circuit. Each time that S1 is closed the time remaining in the cycle is reset to near zero. If the time does run out, closing S1 will restart the cycle.
The following circuits can detect when a train of pulses stops or become to far apart. They can also be use to keep the timer at it zero count time if the input is held in a steady state, this is called 'Negative Recovery'.
The diode across R1 in these circuits causes C1 to quickly discharge when the power to the circuit is switched off. This allows the circuit to be ready for the next cycle in a shorter time.
The next two circuits in this section produce the same result: The timer must be reset manually if it has timed out.
NOTE All of the timers in this circuit will start when power is applied, therefore all but the first timer (A) will need to be Reset for the proper cycle order to be started automatically. (See item 10 in the index of this page for a method of resetting the timers.)
The next diagram gives the current from and the voltage at the RESET terminals of five 555 timer chips from different manufacturers.
The only conclusion to be drawn here is that the RESET terminal should be held below 0.3 Volts to ensure that any of the devices is fully reset.
In the transition voltage range of the RESET terminal mentioned on the diagram, the timers output is neither fully ON or OFF. This can cause high current flows in the timer itself. The voltage at the RESET terminal should pass through this range as quickly as possible to avoid problems.
The next diagram shows the basic current usage's of five 555 timer chips from different manufacturers.
The RESET terminal current draw illustrates the need for a current limiting resistor as shown in some of the preceding circuits. Some devices will not function properly if the current to the RESET terminal is not limited.
The following is a method of preventing a timer from being re-triggered before a certain time period has elapsed.
The next diagram shows the output section of a National Semiconductor LM555 timer. This type of output can either source or sink current and is typical of 555 and 556 timer IC's.
When the output of the timer is HIGH, it can supply current to a load. When the output of the timer is LOW, it can receive current from a load.
Transistor Q3 is actually connected as a diode with the collector not carrying current. Although a 'circuit common' symbol is shown, the collector is not connected to the ground of the timer.
The transistor of the DISCHARGE terminal is tied directly to the output section of the timer.
These circuits will control the application of power to a second circuit using mechanical relays or transistors. Other output control devices could also be used.
A variation on the Power On delay circuits above is a delay after pulses start arriving.
A resistor could be placed across capacitor C1 so that the timer wood be reset if pulses stopped arriving. This resistor should have a resistance of at least three times the value of R1.
The next circuit produces an average duty cycle of 51.5% over the entire resistance range of R2. with a supply voltage of 10 volts.
At a supply voltage of 5 volts the average duty cycle increased to 52.7%. The span of the duty cycle also increased.
The explanations for the circuits on these pages cannot hope to cover every situation on every layout. For this reason be prepared to do some experimenting to get the results you want. This is especially true of circuits such as the "Across Track Infrared Detection" circuits and any other circuit that relies on other than direct electronic inputs, such as switches.
If you use any of these circuit ideas, ask your parts supplier for a copy of the manufacturers data sheets for any components that you have not used before. These sheets contain a wealth of data and circuit design information that no electronic or print article could approach and will save time and perhaps damage to the components themselves. These data sheets can often be found on the web site of the device manufacturers.
Although the circuits are functional the pages are not meant to be full descriptions of each circuit but rather as guides for adapting them for use by others. If you have any questions or comments please send them to the email address on the Circuit Index page.
15 November, 2009
